This invention relates to techniques and structures for providing power routing in partially predesigned integrated circuits, particularly integrated circuits known as gate arrays, wherein the utilization of area, such as macro cells per unit area, is optimized.
The design of integrated circuits has become increasingly automated. To facilitate automation, integrated circuit designers have employed increasingly structured design methods which make use of basic circuit building blocks known as macro cells. In addition to the goal of automation, there has also been a desire to achieve greater signal processing capability in ever decreasing physical areas. One of the limiting factors in achieving higher density in integrated circuit design is the actual physical size of the basic circuit building block (i.e., the macro cell). The size of a macro cell is dependent upon, among other things, the area required for interconnecting the macro cell's internal circuit elements (i.e., macro cell transistors) to implement a particular logic function. This is, in turn, dependent upon the manner in which power is distributed within the macro cell.
In the past, the standard design technique with a double level metal architecture (i.e., an IC structure with two metal levels, M1 and M2, for transverse routing) was to provide power routing by means of an M2 and M1 grid. Connections internal to a macro cell were provided on the first metal level, M1. Power buses which distribute power within a macro cell were also provided on M1. FIGS. 1 and 2 illustrate a double level metal (DLM) integrated circuit 10 designed in accordance with prior art techniques. FIG. 1 shows a portion of the integrated circuit 10. Macro cells 12 are arranged in regions called cell channels 14 and are interconnected by computer aided layout software. Interconnection is achieved by overlaying the macro cells with multiple metal levels containing signal routing resources. Horizontal tracks 16 are disposed on the first metal level, M1, and vertical tracks 18 on the second metal level, M2. Traditionally, metal tracks on adjacent metal levels are disposed transversely with respect to each other. Additionally, metal tracks on metal level M1 intended for interconnecting macro cells are usually located in routing channels 20.
FIG. 2 is a top view of a portion of a macro cell 12 showing the manner in which power is supplied to macro cell transistors 22 according to the prior art. A series of power buses 24 is disposed in the first metal level, M1, and connected to power carrying tracks 26 and 28 which are provided on the second metal level, M2. Contacts between a power bus 24 and particular macro cell transistors 22 are made where necessary to supply the transistor 22 with power. Depending upon the particular designer's needs, many transistors 22 may not have such contacts. Nevertheless, the power buses 24 extend across the entire macro cell 12.
Power buses in gate arrays typically require multiple parallel signal paths in order to handle greater currents and minimize resistive losses. As a result, considerable signal routing resources are used by the power buses, restricting interconnection routing on the M1 level. More importantly with respect to the present invention, interconnection of circuit elements on M1 is further restricted because the power buses extend the entire width of the macro cell, thus blocking desired M1 connections between circuit elements within a macro cell on opposite sides of a power bus.
The addition of a third level of metal, M3, increases the availability of tracks for the interconnection of circuit elements. The use of M3 can result in greater M2 interconnect capability due to the greater amount of resources, but does not reduce the interconnection problems of M1 because the use of M3 resources for internal macro cell interconnections is impracticable. This is because the macro cell interconnections are so tightly congested that the area required for the vias necessary for the use of M3 traces could not be accommodated. Thus there is a need for power routing techniques and structures in integrated circuits wherein the number of macro cell transistor connections per unit area is optimized.